1. Field of the Invention
The present invention generally relates to semiconductor memory devices, and particularly relates to adjustment of timings at which address signals and data signals are latched.
2. Description of the Related Art
FIG. 1 is a block diagram of a command-input and address-input portion of a related-art semiconductor device.
As shown in FIG. 1, command-input signals /CAS (column address strobe), /RAS (row address strobe), /CS (chip select), and /WE (write enable) are input to input buffers 201 through 204. The input buffers 201 through 204 are current-mirror-type buffers, and produce a HIGH-level output or a LOW-level output depending on a comparison between an input signal and a reference voltage level.
The command signals output from the input buffers 201 through 204 are supplied to synchronization buffers 205 through 208, respectively, where synchronization is established between the command signals and a clock signal CLK. The command signals in synchronism with the clock signal CLK are supplied from the synchronization buffers 205 through 208 to a command decoder 209.
The command decoder 209 decodes the command signals /CAS, /RAS, /CS, and /WE so as to output command-decode signals. When the command signals /CAS, /RAS, /CS, and /WE are LOW, HIGH, LOW, and HIGH, respectively, for example, a data-read operation is selected, and the command-decode signals represent the data-read operation. When the command signals /CAS, /RAS, /CS, and /WE are LOW, HIGH, LOW, and LOW, respectively, for example, a data-write operation is selected, and the command-decode signals indicate this fact.
When either a data-write operation or a data-read operation is indicated, an address-input circuit 210 latches address signals at a timing triggered by the command-decode signals supplied from the command decoder 209. The address latched by the address-input circuit 210 is supplied to internal circuits. A control circuit 211 controls the internal circuits so as to achieve the operation which is indicated by the command-decode signals supplied from the command decoder 209. In FIG. 1, signal lines from the command decoder 209 to the address-input circuit 210 and the control circuit 211 are shown in a simplified manner. In actuality, a plurality of signal lines are provided for these paths.
The command decoder 209 is implemented by using a logic circuit of a relatively simple structure, but is designed to reduce an effect of skews between the command signals. Because of this, there is a problem in that a signal delay is relatively large in the command decoder 209. Assume that a two-input NAND circuit is used in the command decoder 209, and receives a first input signal and a second input signal, where the second signal is supposed to change from LOW to HIGH at the same timing at which the first signal changes from HIGH to LOW. If there is an unexpected delay in the change from HIGH to LOW in the first input signal, both signals maintain a HIGH level simultaneously during a short time period. The NAND circuit thus ends up outputting an erroneous signal level. In order to obviate this problem, a gate width of the transistors in the NAND circuit is made narrower, thereby slowing a change in the signal level. This prevents an erroneous signal level from appearing as an output for a short time period.
When a signal delay at the command decoder 209 is elongated because of such a measure as described above to cope with signal skews, a timing at which the address-input circuit 210 latches the address signals is also delayed. Until the address signals are latched and stabilized, a data-write/read operation cannot be started. The delay in the command decoder 209 thus hinders an effort to increase operation speed of the semiconductor memory device.
Accordingly, there is a need for a semiconductor memory device which allows a timing of the address-signal input to be advanced in time so as to achieve high-speed operations.
Similar problems also exist with regard to timings of address-signal decoding, redundant checking, data-signal latching, and burst-length control.
Accordingly, there is a further need for a semiconductor memory device which advances these timings so as to achieve high-speed operations.
Accordingly, it is a general object of the present invention to provide a semiconductor memory device which can satisfy the need described above.
It is another and more specific object of the present invention to provide a semiconductor memory device which allows a timing of the address-signal input to be advanced in time so as to achieve high-speed operations.
In order to achieve the above objects according to the present invention, a semiconductor memory device having an internal circuit includes a command decoder which decodes input-command signals to supply decoded-command signals, an address-latch-signal-generation circuit, operating faster than the command decoder, which decodes the input-command signals to supply an address-latch signal, a control circuit which controls the internal circuit based on the decoded-command signals, and an address-input circuit which latches an address signal in response to the address-latch signal.
In the device described above, the address-latch-signal-generation circuit is provided separately from the command decoder, and operates faster than the command decoder. Therefore, the timing of the address-signal latching becomes earlier than when the command decoder indicates such a timing.
According to one aspect of the present invention, the semiconductor memory described above is such that the command decoder includes a logic circuit operating at a first speed, and the address-latch-signal-generation circuit includes a logic circuit operating at a second speed faster than the first speed.
In the device described above, an operation speed of transistors is faster in the address-latch-signal-generation circuit than in the command decoder. Therefore, the timing of the address-signal latching becomes earlier than when the command decoder indicates such a timing.
According to another aspect of the present invention, the semiconductor memory device described above further includes input buffers which respectively receive the input-command signals from an exterior of the semiconductor memory device, first synchronization buffers which respectively receive the input-command signals from the input buffers, and supply the input-command signals to the command decoder in synchronism with a clock signal, a second synchronization buffer which receives the address-latch signal from the address-latch-signal-generation circuit, and supplies the address-latch signal to the address-input circuit in synchronism with the clock signal, wherein the address-latch-signal-generation circuit receives the input-command signals directly from the input buffers.
In the device described above, when a timing to establish synchronization with the clock signal is used as a reference, a timing at which the address-latch signal is input to the address-input circuit is earlier than a timing at which the decoded-command signals are input to the control circuit.
According to another aspect of the present invention, the semiconductor memory device described above is such that the first speed is set such that skews are sufficiently removed from the input-command signals when the command decoder decodes the command-input signals.
In the device described above, anti-skew measures are taken in the command decoder, so that malfunction of the semiconductor memory device can be prevented.
According to another aspect of the present invention, the semiconductor memory device described above is such that the second speed is faster than such speed as at least required to sufficiently remove the skews.
In the device described above, the anti-skew measures are put in place for the command decoder, while no such measures are taken for the address-latch-signal-generation circuit, which is thus free from a speed limit. Therefore, the timing of address input is made earlier, and, at the same time, malfunction of the semiconductor memory device can be prevented.
Also, in order to achieve the forgoing objects, a semiconductor memory device includes a command decoder which decodes input-command signals to supply decoded-command signals for controlling operations of the semiconductor memory device, and an address-latch-signal-generation circuit which decodes the input-command signals to supply an address-latch signal used for latching an address, wherein the address-latch-signal-generation circuit operates at a faster speed than the command decoder.
In the device described above, the address-latch-signal-generation circuit is provided separately from the command decoder, and operates faster than the command decoder. Therefore, the timing of the address-signal latching becomes earlier than when the command decoder indicates such a timing.
According to another aspect of the present invention, the semiconductor memory device described above is such that the command decoder operates at such speed as to sufficiently remove skews from the command-input signals when decoding the command-input signals, and the address-latch-signal-generation circuit operates at a speed faster than such speed as at least required to sufficiently remove the skews.
In the device described above, the anti-skew measures are put in place for the command decoder, while no such measures are taken for the address-latch-signal-generation circuit, which is thus free from a speed limit. Therefore, the timing of address input is made earlier, and, at the same time, malfunction of the semiconductor memory device can be prevented
Further, in order to achieve the forgoing objects, a semiconductor memory device includes a command decoder which receives input-command signals after the input-command signals are synchronized with a clock signal, and decodes the input-command signals to supply decoded-command signals for controlling the semiconductor memory device, and an address-latch-signal-generation circuit which receives the input-command signals before the input-command signals are synchronized with the clock signal, and decodes the input-command signals to supply an address-latch signal used for latching an address.
In the device described above, a synchronization with the clock signal is established at a stage preceding the command decoder, whereas it is established at a stage following the address-latch-signal-generation circuit. When a timing to establish a synchronization with the clock signal is used as a reference, therefore, a timing at which the address-latch signal is input to the address-input circuit is earlier than a timing at which the decoded-command signals are input to the control circuit.
It is yet another object of the present invention to provide a semiconductor memory device which advances timings of address-signal decoding, redundant checking, data-signal latching, and burst-length control so as to achieve high-speed operations.
In order to achieve some of the above objectives, a semiconductor memory device includes a command decoder which decodes input-command signals to supply decoded-command signals, an address decoder which decodes input-address signals to supply decoded-address signals, and an address input circuit which latches the decoded-address signals supplied from the address decoder in response to at least one of the decoded-command signals.
In the device described above, the address decoder is provided at a stage preceding the address-input circuit, so that a time required for a decoding process in the address decoder can be ignored when a timing of the address-signal latching is used as a reference. Namely, the address data output from the address-input circuit can be immediately supplied to the internal circuit without any intervening cause of delay. This makes it possible to perform data-write operations and data-read operations at an earlier timing than otherwise it would be, thereby achieving a higher operation speed of the semiconductor memory device.
According to another aspect of the present invention, a semiconductor memory device includes a command decoder which decodes input-command signals to supply decoded-command signals, an address decoder which decodes input-address signals to supply decoded-address signals, an address-latch-signal-generation circuit which operates at a faster speed than the command decoder, and decodes the input-command signals to supply an address-latch signal, and an address-input circuit which latches the decoded-address signals supplied from the address decoder in response to the address-latch signal.
In the device described above, the address decoder is provided at a stage preceding the address-input circuit, so that a time required for a decoding process in the address decoder can be ignored. Also, the address-latch-signal-generation circuit is separately provided, and operates faster than the command decoder. Therefore, the timing of the address-signal latching becomes earlier than when the command decoder indicates such a timing.
According to another aspect of the present invention, a semiconductor memory device includes a command decoder which decodes input-command signals to supply decoded-command signals, buffers which receive input-address signals, an address-input circuit which latches the input-address signals supplied from the buffers in response to at least one of the decoded-command signals, a redundancy-check unit which receives the input-address signals from the buffers, and checks whether the input-address signals indicate a redundant address, and an address decoder which receives the input-address signals from the address-input circuit and redundancy-check results from the redundancy-check unit, and decodes the input-address signals to supply decoded-address signals in accordance with the redundancy-check results.
In the device described above, a redundancy check of the address signal is performed at least no later than the operation of the address-input circuit. Namely, the redundancy check of the address signal can be completed before the address-input circuit latches the address signals upon a trigger from the command decoder, which has a relatively long time delay. Therefore, a timing at which the decoded-address signals are output can be advanced in time.
According to another aspect of the present invention, the semiconductor memory device described above is such that the address decoder includes an address pre-decoder which receives the input-address signals from the address-input circuit and the redundancy-check results from the redundancy-check unit, and decodes the input-address signals to supply pre-decoded-address signals in accordance with the redundancy-check results, and a decoder which decodes the pre-decoded-address signals to supply the decoded-address signals.
In the device described above, a redundancy check of the address signal is performed at least no later than the operation of the address-input circuit. Namely, the redundancy check of the address signal as well as the pre-decode operation can be completed before the address-input circuit latches the address signals upon a trigger from the command decoder, which has a relatively long time delay. Therefore, a timing at which the decoded-address signals are output can be advanced in time.
According to another aspect of the present invention, a semiconductor memory device having an internal circuit includes a command decoder which decodes input-command signals to supply decoded-command signals, a data-acquisition-signal-generation circuit, operating faster than the command decoder, which decodes the input-command signals to supply a data-acquisition signal, a control circuit which controls the internal circuit based on the decoded-command signals, and a data-acquisition circuit which receives an input-data signal, and supplies the input-data signal to an output thereof in response to the data-acquisition signal.
In the device described above, the data-acquisition-signal-generation circuit is provided separately from the command decoder, and operates faster than the command decoder. Therefore, the timing of the data-signal acquisition becomes earlier than when the command decoder indicates such a timing.
According to another aspect of the present invention, the semiconductor memory device described above further includes a data-write circuit which writes the input-data supplied from the data-acquisition circuit in the internal circuit, the control circuit further controlling the data-write circuit based on the decoded-command signals.
In the device described above, the data-write circuit is controlled by the control circuit, so that no malfunction is expected as long as anti-skew measures are put in place in the command decoder. Because of this, the data-acquisition-signal-generation circuit can benefit from use of a faster logic circuit which ignores anti-skew consideration.
According to another aspect of the present invention, a semiconductor memory device includes a first circuit which supplies a burst-start-address-latch pulse in synchronism with a clock signal, the burst-start-address-latch pulse being used for latching a burst-start address supplied from an exterior of the semiconductor memory device, and a second circuit which supplies internally-generated-address-latch pulses in synchronism with the clock signal, the internally-generated-address-latch pulses being used for latching internal addresses which are internally generated to follow the burst-start address, wherein the second circuit includes a burst-length-control circuit which generates a period indicating signal for indicating a time period during which the internally-generated-address-latch pulses are generated, and a synchronization circuit which generates the internally-generated-address-latch pulses by synchronizing the period indicating signal to the clock signal.
In the device described above, the burst-length-control circuit is situated at a stage preceding the synchronization circuit, so that the burst-start-address-latch pulse and the internally-generated-address-latch pulses are supplied at a timing immediately following the clock synchronization.
According to another aspect of the present invention, the semiconductor memory device described above is such that the burst-length-control circuit includes a logic circuit which generates the period indicating signal based on input-command signals and other signals, the other signals including a signal indicative of an end of a burst period and a signal indicative of an active state which is set to the semiconductor memory device by the input-command signals.
In the device described above, the burst-length-control circuit can be implemented based on a simple logic circuit.
According to another aspect of the present invention, the semiconductor memory device described above is such that the first circuit includes a logic circuit which generates a burst-start signal when the input-command signals show a predetermined combination of signal levels, and a synchronization circuit which generates the burst-start-address-latch pulse by synchronizing the burst-start signal to the clock signal.
In the device described above, the circuit for generating the burst-start-address-latch pulse can be implemented based on a simple logic circuit.
Other objects and further features of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings.